This invention relates generally to arrays of non-volatile memory cells which each includes a field effect transistor with a floating gate, and, more specifically, to EEPROM and flash EEPROM arrays and processes of forming them.
Field effect transistors having floating (unconnected) gates have long been utilized to form a non-volatile, semiconductor memory. Electrons are moved onto or removed from the floating gate of a given transistor memory cell in order to program or erase its state. The state of such a transistor memory cell determined by applying a voltage across its source and drain and then measuring the current which passes through the transistor. The programmed level of charge on the floating gate is retained for a long period of time, essentially indefinitely. Memory arrays of such transistor cells are commonly available in various forms, such as PROMs, EPROMs, EEPROMs and flash EEPROMs. Currently, flash EEPROM technology is being used for large capacity semiconductor non-volatile memory, either in place of, or in combination with, a magnetic disk drive memory system.
Typically, such a semiconductor memory system is made up of a number of integrated circuit chips that each contain a two dimensional array of EEPROM cells, plus other integrated circuit chips providing a controller and other system operating support. A typical memory array integrated circuit chip includes elongated, spaced apart source and drain regions formed in a surface of a semiconductor substrate. These source and drain regions form the bit lines of the memory. A two dimensional array of floating gates has each floating gate positioned in a channel region between adjacent source and drain regions. An elongated control gate is positioned over each row of floating gates in a direction transverse to the source and drain regions. The control gates are the word lines of the memory array.
One type of cell used in such a memory array extends each of its floating gates over only part of its channel between the source and drain regions, while the control gate is positioned over the remaining portion of the channel. This is termed a "split-channel" type of EEPROM cell and effectively connects a select transistor in series with the floating gate transistor in order to isolate the floating gate transistor from the bit lines when its control gate (word line) is not active. An alternative type of EEPROM cell extends its control gate completely across the channel region, thus eliminating the select transistor and allowing the memory cell to be made smaller. However, the absence of the select transistor in each cell places additional constraints on operating a memory array of such cells.
One class of EEPROM devices employs an erase gate positioned adjacent the floating gate of each cell, with a thin dielectric therebetween, in order to transfer electrons from the floating gate to the erase gate when all the relative voltages are appropriately set. Flash EEPROM systems use a common erase gate for a sector or other block of cells, thus enabling their simultaneous erasure in a "flash." An alternative class of EEPROM devices does not use the separate erase gate, but rather removes the electrons from the floating gate through the substrate when all the appropriate voltages are set. In such flash EEPROM systems, the sectors or other blocks of cells are isolated from one another on the substrate in order that the individual blocks may be selectively and individually erased.
Regardless of which type or class of EEPROM cell is being utilized, a great deal of development effort is being directed to reducing the size of the individual memory cells, and thus increasing their density, in order to increase the memory capacity of each integrated circuit chip. It is desired that the capacity of an entire memory system of a given physical size, such one as formed on the currently popular PCMCIA plug-in cards, be increased. Therefore, it is the principal object of the present invention to provide cell structures and processes of forming them which reduces the size of the individual cells and thus increases the storage capacity of memory systems utilizing them.
It is another principal object of the present invention to form elements of the memory cells and peripheral transistors on the same integrated circuit chip with a resolution that is greater than that which results from using of state of the art processing techniques.
A further object of the present invention is to provide a flash EEPROM array with a longer cycle life.
It is also an object of the present invention to provide a flash EEPROM array which can be erased with reduced voltages.
Another object of the present invention is to improve the process by which the peripheral transistors and other circuit elements surrounding an array of memory cells are formed.
Yet another object of the present invention is to provide an improved coordination in the processes of forming memory cells and peripheral transistors as part of a common integrated circuit.
Still another object of the present invention is to provide improved techniques of forming field (thick) oxide in integrated circuits.
Also, it is an object of the present invention to be able to form on a rough surface a thin layer of material which has a smooth top surface.